View M5M467405DTP-5S_3160906.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s standard 32 pin soj, 32 pin tsop standard 50 pin soj, 50 pin tsop single 3.3 0.3v supply low stand-by power dissipation 1.8mw (max) lvcmos input level low operating power dissipation m5m467405dxx-5,5s / m5m467805dxx-5,5s 360.0mw (max) m5m467405dxx-6,6s / m5m467805dxx-6,6s 324.0mw (max) m5m465405dxx-5,5s / m5m465805dxx-5,5s 468.0mw (max) m5m465405dxx-6,6s / m5m465805dxx-6,6s 432.0mw (max) m5m465165dxx-5,5s 504.0mw (max) m5m465165dxx-6,6s 468.0mw (max) self refresh capability* self refresh current 400? (max) edo mode , read-modify-write, cas before ras refresh, hidden refresh capabilities early-write mode , oe and w to control output buffer impedance all inputs, outputs lvttl compatible and low capacitance :applicable to self refresh version(m5m467405/465405/467805/465805/465165dj,dtp-5s,-6s:option) only application main memory unit for computers, microcomputer memory, refresh memory for crt description the m5m467405/465405dj,dtp is a 16777216-word by 4-bit, m5m467805/465805dj,dtp is a 8388608-word by 8-bit, and m5m465165dj,dtp is a 4194304-word by 16-bit dynamic rams, fabricated with the high performance cmos process, and are suitable for large-capacity memory systems with high speed and low power dissipation. * address m5m465405dxx m5m467405dxx part no. xx=j,tp features type name m5m467405dxx-5,5s m5m467805dxx-5,5s m5m467405dxx-6,6s m5m467805dxx-6,6s m5m465405dxx-5,5s m5m465805dxx-5,5s m5m465405dxx-6,6s m5m465805dxx-6,6s access time (max.ns) ras access time (max.ns) cas (max.ns) access time address time (min.ns) cycle dissipa- (typ.mw) power tion 50 60 50 13 15 13 25 30 25 84 104 84 300 250 390 13 15 13 access time (max.ns) oe 60 15 30 104 325 15 type name access time (max.ns) ras access time (max.ns) cas (max.ns) access time address time (min.ns) cycle access time (max.ns) oe m5m465165dxx-6,6s m5m465165dxx-5,5s 50 60 13 15 25 30 84 104 13 15 dissipa- (typ.mw) power tion 420 390 (m5m467405dxx/m5m465405dxx/m5m467805dxx/m5m465805dxx) (m5m465165dxx) m5m465805dxx m5m467805dxx m5m465165dxx a0-a12 row add. col. add. refresh refresh cycle ras only ref,normal r/w cbr ref,hidden ref ras only ref,normal r/w cbr ref,hidden ref a0-a10 a0-a11 a0-a11 8192/64ms 4096/64ms 4096/64ms 8192/128ms 4096/128ms 4096/128ms normal s-version a0-a12 ras only ref,normal r/w cbr ref,hidden ref ras only ref,normal r/w cbr ref,hidden ref a0-a9 a0-a11 a0-a10 8192/64ms 4096/64ms 4096/64ms 8192/128ms 4096/128ms 4096/128ms ras only ref,normal r/w cbr ref,hidden ref a0-a11 a0-a9 4096/64ms 4096/128ms 1 preliminary some of contents are subject to change without notice.
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s m5m465405dj m5m467405dj outline 32p0n (400mil soj) vcc dq 2 w ras a 11 a 10 a 0 a 1 a 2 a 3 vcc vss dq 4 dq 3 cas oe a 9 a 8 a 7 a 6 a 5 a 4 vss nc nc nc nc a 12 /nc(note) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dq 1 nc nc nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc note a12...m5m467405dxx, nc...m5m465405dxx no connection : : m5m465405dtp m5m467405dtp outline 32p3n (400mil tsop normal bend) vcc dq 2 w ras a 11 a 10 a 0 a 1 a 2 a 3 vcc vss dq 4 dq 3 cas oe a 9 a 8 a 7 a 6 a 5 a 4 vss nc nc nc nc a 12 /nc(note) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dq 1 nc nc nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 pin configuration (top view) pin description pin name a 0 -a 12 dq1-dq4 ras cas w oe vcc vss function address inputs data inputs / outputs row address strobe input column address strobe input write control input power supply (+3.3v) ground (0v) output enable input nc no connection pin name a 0 -a 11 dq1-dq16 ras ucas w oe vcc vss function address inputs data inputs / outputs row address strobe input column address strobe input write control input power supply (+3.3v) ground (0v) output enable input nc no connection upper byte control lcas column address strobe input lower byte control pin name a 0 -a 12 dq1-dq8 ras cas w oe vcc vss function address inputs data inputs / outputs row address strobe input column address strobe input write control input power supply (+3.3v) ground (0v) output enable input nc no connection m5m467405dxx / m5m465405dxx m5m467805dxx / m5m465805dxx m5m465165dxx xx=j, tp m5m467400/465400dj, dtp 2
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s nc note a12...m5m467800dxx, nc...m5m465800dxx no connection : : m5m465805dj m5m467805dj outline 32p0n (400mil soj) vcc dq 2 w ras a 11 a 10 a 0 a 1 a 2 a 3 vcc vss dq 8 dq 7 cas oe a 9 a 8 a 7 a 6 a 5 a 4 vss a 12 /nc(note) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dq 1 nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dq 4 dq 3 dq 6 dq 5 vss vcc m5m465805dtp m5m467805dtp outline 32p3n (400mil tsop normal bend) vcc dq 2 w ras a 11 a 10 a 0 a 1 a 2 a 3 vcc vss cas oe a 9 a 8 a 7 a 6 a 5 a 4 vss a 12 /nc(note) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dq 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dq 8 dq 7 nc dq 4 dq 3 dq 6 dq 5 vss vcc nc : no connection outline 50p0g (400mil soj) 11 25 24 23 22 1 10 2 3 4 5 6 9 7 8 36 35 34 33 40 41 42 15 16 20 17 19 18 21 28 27 26 29 30 31 32 43 44 45 46 47 48 49 50 12 nc ucas oe a 9 a 8 a 7 a 6 a 5 a 4 a 0 a 1 a 2 a 3 nc a 11 a 10 lcas dq 9 dq 1 dq 2 dq 3 dq 4 vss dq 8 dq 7 dq 6 dq 5 dq 15 dq 14 dq 13 dq 10 dq 11 dq 12 dq 16 nc nc 12 vcc 13 14 37 38 39 vss w ras nc nc nc nc nc m5m465165dj vcc vcc vcc vss vss outline 50p3g (400mil tsop normal bend) 11 25 24 23 22 1 10 2 3 4 5 6 9 7 8 36 35 34 33 40 41 42 15 16 20 17 19 18 21 28 27 26 29 30 31 32 43 44 45 46 47 48 49 50 12 nc ucas oe a 9 a 8 a 7 a 6 a 5 a 4 a 0 a 1 a 2 a 3 nc a 11 a 10 lcas dq 9 dq 1 dq 2 dq 3 dq 4 vss dq 8 dq 7 dq 6 dq 5 dq 15 dq 14 dq 13 dq 10 dq 11 dq 12 dq 16 nc nc 12 vcc 13 14 37 38 39 vss w ras nc nc nc nc nc m5m465165dtp vss vss vcc vcc vcc pin configuration (top view) m5m465165dj, dtp pin configuration (top view) m5m467805/465805dj, dtp 3
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s function the m5m467405(805)/465405(805,165)dj, dtp provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., edo mode, cas before ras refresh, and delayed-write. the input conditions for each are shown in table 1. table 1 input conditions for each mode operation ras cas oe inputs input/output refresh remark w row address address column input output read write (early write) write (delayed write) read-modify-write act act act act act act act act nac act act act act dnc dnc act apd apd apd apd apd apd apd apd opn vld opn ivd vld edo mode identical standby hidden refresh act act nac act act dnc nac dnc act dnc dnc dnc dnc dnc dnc dnc dnc opn dnc dnc vld opn opn yes yes no cas before ras refresh no no no no vld vld vld m5m467405dxx / m5m465405dxx / m5m467805dxx / m5m465805dxx note : act : active, nac : nonactive, dnc : don' t care, vld : valid, ivd : invalid, apd : applied, opn : open operation ras inputs ucas lower byte read lower byte write word write stand-by hidden refresh act act act act nac act act dnc oe w nac dnc dnc act dnc ras-only refresh cas before ras refresh act act dnc lcas upper byte read nac nac nac act word read act act act nac act upper byte write act act act act nac nac act act act nac act nac act nac act nac nac dnc nac act act act act dnc dnc input/output dq1~dq8 opn vld opn opn dq9~dq16 vld vld vld din dnc din dnc din din opn vld vld opn opn opn opn m5m465165dxx row address address column apd apd apd apd apd apd apd apd dnc dnc dnc dnc dnc dnc dnc apd apd apd apd refresh remark yes yes no edo mode identical no no no no no no yes ras-only refresh act nac dnc dnc apd dnc opn opn yes apd 4 nac
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s block diagram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 address inputs clock generator circuit column decoder sense refresh amplifier & i /o control row decoder row & column address buffer memory cell (67108864 bits) (4) data in buffers (4) data out buffers vcc (3.3v) vss (0v) dq1 oe dq2 dq3 dq4 data inputs / outputs output enable input column address strobe input row address strobe input write control input cas ras w a0~a11 a0~ a12 (note) (note) note refer to page 1 (address) : a12 (note) block diagram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 address inputs clock generator circuit column decoder sense refresh amplifier & i /o control row decoder row & column address buffer memory cell (67108864 bits) (8) data in buffers (8) data out buffers vcc (3.3v) vss (0v) dq3 oe dq4 dq5 dq6 data inputs / outputs output enable input column address strobe input row address strobe input write control input cas ras w a0~a10 a0~ a12 dq2 dq1 dq7 dq8 (note) (note) note refer to page 1 (address) : a12 (note) m5m467405dxx / m5m465405dxx m5m467805dxx / m5m465805dxx 5
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s lower byte control column address strobe input upper byte control column address strobe input block diagram clock generator circuit v cc (3.3v) v ss (0v) row address strobe input ras w a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 address inputs column decoder sense refresh amplifier & i /o control row decoder row & column address buffer memory cell (67108864bits) dq 1 oe dq 2 dq 8 output enable input a 0 ~a 9 a 0 ~ a 11 ucas (8)lower data in buffers (8)lower data out buffers (8)upper data in buffers (8)upper data out buffers lower data inputs / outputs dq 9 dq 10 dq 16 lower upper a 11 a 10 lcas upper data inputs / outputs m5m465165dxx write control input 6
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 7 absolute maximum ratings symbol vcc vi v0 i0 pd topr tstg parameter conditions ratings unit v v v ma mw c c -0.5 4.6 -0.5 4.6 -0.5 4.6 50 1000 0 70 -65 150 with respect to vss ta=25 c supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature recommended operating conditions unit limits min nom max v v v v 3.6 0 vcc+0.3 0.8 3.3 0 3.0 0 2.0 -0.3 parameter supply voltage supply voltage high-level input voltage, all inputs low-level input voltage, all inputs vcc symbol vss v ih v il (ta=0 70 , unless otherwise noted) (note 1) c note 1 : all voltage values are with respect to vss. electrical characteristics (ta=0 70 , vcc=3.3 0.3v, vss=0v, unless otherwise noted) (note 2) c symbol v oh v ol i oz i i i cc1 (av) high-level output voltage parameter limits min max unit typ test conditions low-level output voltage off-state output current input current average supply current from vcc operating (note 3,4,5) m5m467405d-5,5s m5m467805d-5,5s m5m467405d-6,6s m5m467805d-6,6s i oh =-2ma i ol =2ma q floating 0v v out vcc 0v vin vcc+0.3v, other input pins=0v ras, cas cycling t rc =t wc =min. output open note 2: current flowing into an ic is positive, out is negative. 3: icc1 (av) , icc4 (av) and icc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4: icc1 (av) and icc4 (av) are dependent on output loading. specified values are obtained with the output open. 5: column address can be changed once or less while ras=v il and cas=v ih . v v ma vcc 0.4 10 10 100 90 2.4 0 -10 -10 [m5m467405d / m5m467805d] ~ ~ ~ ~ ~ ~ ~ ? ? ras= cas =v ih, output open 1 m5m467405d-5,5s -6,6s ras= cas 3 vcc -0.2v,output open ma 0.5 m5m467405d-5,6 m5m467805d-5,6 m5m467405d-5s,6s m5m467805d-5s,6s 0.3 i cc2 (av) average supply current from vcc stand-by i cc4 (av) (note 3,4,5) average supply current from vcc edo-mode m5m467405d-5,5s m5m467805d-5,5s ras=v il, cas cycling t hpc =min. output open ma ma 100 m5m467405d-6,6s m5m467805d-6,6s 90 i cc6 (av) (note 3,5) average supply current from vcc cas before ras refresh mode m5m467405d-5,5s m5m467805d-5,5s 130 m5m467405d-6,6s m5m467805d-6,6s 120 cas before ras refresh cycling t rc =min. output open (note 6) m5m467805d-5,5s -6,6s
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 8 electrical characteristics (ta=0 70 , vcc=3.3 0.3v, vss=0v, unless otherwise noted) (note 2) c [m5m465405d / m5m465805d] symbol v oh v ol i oz i i i cc1 (av) high-level output voltage parameter low-level output voltage off-state output current input current average supply current from vcc operating (note 3,4,5) m5m465405d-5,5s m5m465805d-5,5s m5m465405d-6,6s m5m465805d-6,6s m5m465405d-5,5s -6,6s m5m465405d-5,6 m5m465805d-5,6 m5m465405d-5s,6s m5m465805d-5s,6s i cc2 (av) average supply current from vcc stand-by i cc4 (av) (note 3,4,5) average supply current from vcc edo-mode m5m465405d-5,5s m5m465805d-5,5s m5m465405d-6,6s m5m465805d-6,6s i cc6 (av) (note 3,5) average supply current from vcc cas before ras refresh mode m5m465405d-5,5s m5m465805d-5,5s m5m465405d-6,6s m5m465805d-6,6s (note 6) m5m465805d-5,5s -6,6s limits min max unit typ test conditions i oh =-2ma i ol =2ma q floating 0v v out vcc 0v vin vcc+0.3v, other input pins=0v ras, cas cycling t rc =t wc =min. output open v v ma vcc 0.4 10 10 130 2.4 0 -10 -10 ? ? ras= cas =v ih, output open 1 ras= cas 3 vcc -0.2v,output open ma 0.5 0.3 ras=v il, cas cycling t hpc =min. output open ma ma 100 90 130 120 cas before ras refresh cycling t rc =min. output open 120 [m5m465165d] symbol v oh v ol i oz i i i cc1 (av) i cc2 (av) high-level output voltage parameter low-level output voltage off-state output current input current average supply current from vcc operating (note 3,4,5) average supply current from vcc stand-by m5m465165d-5,5s m5m465165d-6,6s i cc4 (av) i cc6 (av) average supply current from vcc edo-mode (note 3,4,5) average supply current from vcc cas before ras refresh mode (note 3,5) m5m465165d-5,5s m5m465165d-6,6s m5m465165d-5,5s m5m465165d-6,6s limits min max unit typ test conditions i oh =-2ma i ol =2ma ras= cas =v ih, output open v v ma ma vcc 0.4 10 10 140 130 1 0.5 2.4 0 -10 -10 ras, cas cycling output open t rc =t wc =min. q floating 0v v out vcc 0v vin vcc+0.3v, other input pins=0v ras= cas vcc -0.2v, output open 3 ma ma 120 110 140 130 cas before ras refresh cycling t rc =min. output open ras=v il, cas cycling output open t hpc =min. ? ? 0.3 m5m465165d-5,5s -6,6s m5m465165d-5,6 m5m465165d-5s,6s (note 6) ~
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 9 switching characteristics (ta=0 70 , vcc=3.3 0.3v, vss=0v, unless otherwise noted , see notes 6,14,15) c parameter symbol limits unit m5m46x405d-5,5s m5m46x805d-5,5s m5m465165d-5,5s m5m46x405d-6,6s m5m46x805d-6,6s m5m465165d-6,6s access time from cas access time from ras column address access time t cac ns ns ns ns ns 15 30 33 60 13 25 28 50 t rac t aa t cpa t oea access time from cas precharge (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) access time from oe 15 13 min max min max 5 5 t clz t oez (note 12) output disable time after oe high 15 13 ns ns t wez output disable time after w high t off output disable time after cas high t rez output disable time after ras high 13 13 13 15 15 15 ns ns ns (note 12) (note 12,13) (note 12,13) output low impedance time from cas low (note 7) ns t ohc output hold time from cas ns t ohr output hold time from ras (note 13) 5 5 5 5 ~ note 6: an initial pause of 500? is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing ras-only refresh or cas before ras refresh). note the ras may be cycled during the initial pause. and any eight initialization cycles are required after prolonged periods (greater than 64 ms) of ras inactivity before proper device operation is achieved. 7: measured with a load circuit equivalent to voh=2.4v(ioh=-2ma) / vol=0.4v(iol=2ma) loads and 100pf. the reference levels for measuring of output signals are voh=2.0v and vol=0.8v. 8: assumes that t rcd t rcd(max) and t asc t asc(max) and t cp t cp(max). 9: assumes that t rcd t rcd(max) and t rad t rad(max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac will increase by amount that t rcd exceeds the value shown. 10: assumes that t rad t rad(max) and t asc t asc(max). 11: assumes that t cp t cp(max) and t asc t asc(max). 12: t oez(max), t wez(max) , t off(max) and t rez(max) defines the time at which the output achieves the high impedance state (i out 10 a) and is not reference to v oh(min) or v ol(max). 13: output is disabled after both ras and cas go to high. 3 3 3 3 3 capacitance (ta=0 70 , vcc=3.3 0.3v, vss=0v, unless otherwise noted) c limits min max unit typ pf pf pf pf pf pf input capacitance,address inputs c i (a) c i (oe) c i (ras) c i (w) c i (cas) c i / o symbol parameter test conditions input capacitance, oe input input capacitance, write control input input capacitance, ras input input capacitance, cas input input/output capacitance, data ports 5 7 7 7 7 v i =vss f=1mh z vi=25mvrms 7 ~
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s timing requirements (for read, write, read-modify-write ,refresh, and edo mode cycles) (ta=0 70 , vcc=3.3 0.3v, vss=0v, unless otherwise noted see notes 14,15) c read and refresh cycles parameter symbol limits unit note 22: either t rch or t rrh must be satisfied for a read cycle. read cycle time ras low pulse width cas low pulse width t rc 0 t ras t cas t csh t rsh t rcs cas hold time after ras low read setup time before cas low read hold time after cas high (note 22) t rch t rrh (note 22) 0 t ral t orh ras hold time after cas low read hold time after ras high column address to ras hold time ras hold time after oe low 10000 10000 10000 10000 84 50 8 35 13 0 25 13 0 0 104 60 10 40 15 0 30 15 t cal column address to cas hold time 13 18 ns ns ns ns ns ns ns ns min max min max ns ns ns t och 13 15 ns cas hold time after oe low note 14: the timing requirements are assumed t t =2ns. 15: v ih(min) and v il(max) are reference levels for measuring timing of input signals. 16: t rcd(max) is specified as a reference point only. if t rcd is less than t rcd(max), access time is t rac. if t rcd is greater than t rcd(max), access time is controlled exclusively by t cac or t aa. 17: t rad(max) is specified as a reference point only. if t rad t rad(max) and t asc t asc(max), access time is controlled exclusively by t aa. 18: t asc(max) is specified as a reference point only. if t rcd t rcd(max) and t asc t asc(max), access time is controlled exclusively by t cac. 19: either t dzc or t dzo must be satisfied. 20: either t rdd or t cdd or t odd or t wed must be satisfied. 21: t t is measured between v ih(min) and v il(max). 3 3 3 ~ parameter symbol limits unit m5m46x405d-5,5s m5m46x805d-5,5s m5m465165d-5,5s m5m46x405d-6,6s m5m46x805d-6,6s m5m465165d-6,6s refresh cycle time t ref 64 64 ms min max min max ras high pulse width delay time, ras low to cas low t rp t rcd t crp t rpc t cpn delay time, cas high to ras low delay time, ras high to cas low cas high pulse width (note21) (note16) (note17) (note18) 45 30 0 40 13 50 14 5 10 12 10 10 0 0 1 37 25 0 30 10 50 14 5 8 10 8 8 0 0 1 t rad t asr t asc t rah t cah t t column address delay time from ras low row address setup time before ras low column address setup time before cas low row address hold time after ras low column address hold time after cas low transition time (note19) (note20) (note19) (note20) delay time, data to cas low delay time, data to oe low delay time, cas high to data delay time, oe high to data t dzc t dzo t cdd t odd 0 0 0 0 15 13 15 13 (note20) delay time, ras high to data t rdd 15 13 ns ns ns ns ns ns ns ns ns 128 128 ms refresh cycle time (s-version only) t ref ns ns ns ns ns ns ns ns 15 13 (note20) delay time, w low to data t wed 10 m5m46x405d-5,5s m5m46x805d-5,5s m5m465165d-5,5s m5m46x405d-6,6s m5m46x805d-6,6s m5m465165d-6,6s
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 11 write cycle (early write and delayed write) parameter symbol read-write and read-modify-write cycles limits parameter symbol limits unit m5m46x405d-5,5s m5m46x805d-5,5s m5m465165d-5,5s m5m46x405d-6,6s m5m46x805d-6,6s m5m465165d-6,6s oe hold time after w low read write/read modify write cycle time ras low pulse width cas low pulse width t rwc t ras t cas t csh t rsh t rcs cas hold time after ras low ras hold time after cas low read setup time before cas low (note23) (note24) 44 44 0 32 77 47 38 109 38 70 0 28 65 40 t cwd t rwd t awd delay time, cas low to w low delay time, ras low to w low delay time, address to w low (note24) (note24) 10000 10000 10000 10000 75 133 89 82 ns ns ns ns ns ns ns ns ns min max min max ns 15 13 t oeh write cycle time ras low pulse width cas low pulse width t wc 8 t ras t cas t csh t rsh t wcs cas hold time after ras low write setup time before cas low write hold time after cas low (note 24) t wch t cwl 0 t rwl t wp t ds ras hold time after cas low cas hold time after w low 10000 10000 10000 10000 84 50 8 35 13 8 0 10 0 104 60 10 40 15 10 0 8 10 t dh ras hold time after w low data setup time before cas low or w low data hold time after cas low or w low write pulse width ns ns ns ns ns ns ns ns unit min max min max ns ns ns ns 8 10 8 10 note 23: t rwc is specified as t rwc(min) =t rac(max) +t odd(min) +t rwl(min) +t rp(min) +4t t. 24: t wcs , t cwd , t rwd and t awd and, t cpwd are specified as reference points only. if t wcs t wcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if t cwd t cwd(min), t rwd t rwd (min), t awd t awd(min) and t cpwd t cpwd(min) (for edo mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) is satisfied, the dq (at access time and until cas or oe goes back to v ih ) is indetermi- nate. 3 3 3 3 3 m5m46x405d-5,5s m5m46x805d-5,5s m5m465165d-5,5s m5m46x405d-6,6s m5m46x805d-6,6s m5m465165d-6,6s
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 12 cas before ras refresh cycle (note 28) note 28: eight or more cas before ras cycles instead of eight ras cycles are necessary for proper operation of cas before ras refresh mode. edo mode cycle (read, early write, read-write, read-modify-write cycle, read write mix cycle, hi-z control by oe or w) (note 25) parameter symbol limits unit parameter symbol limits unit cas setup time before ras low t csr t chr t rsr t rhr cas hold time after ras low read setup time before ras low read hold time after ras low 5 10 10 10 5 10 10 10 ns ns ns ns min max min max edo mode read/write cycle time ras low pulse width for read write cycle cas high pulse width t hpc t ras t cp t cprh t cpwd ras hold time after cas precharge (note26) (note27) 28 20 8 43 delay time, cas precharge to w low (note24) 100000 33 25 10 50 100000 13 16 t hprwc edo mode read write / read modify write cycle time 55 66 t chol hold time to maintain the data hi-z until cas access 7 7 t oepe t wpe oe pulse width (hi-z control) 7 7 w pulse width (hi-z control) 7 7 ns ns ns ns ns ns ns ns min max min max ns ns 5 5 t doh output hold time from cas low delay time, cas low to w low after read 28 32 t hcwd delay time, address to w low after read delay time, cas precharge to w low after read delay time, cas low to oe high after read delay time, address to oe high after read delay time, cas precharge to oe high after read t hawd t hpwd t hcod t haod t hpod 40 47 43 50 13 15 25 30 28 33 ns ns ns ns ns ns 65 77 note 25: all previously specified timing requirements and switching characteristics are applicable to their respective edo mode cycle. 26: t ras(min) is specified as two cycles of cas input are performed. 27: t cp(max) is specified as a reference point only. if t cp t cp(max) , access time is controlled exclusively by tcac. 3 m5m46x405d-5,5s m5m46x805d-5,5s m5m465165d-5,5s m5m46x405d-6,6s m5m46x805d-6,6s m5m465165d-6,6s m5m46x405d-5,5s m5m46x805d-5,5s m5m465165d-5,5s m5m46x405d-6,6s m5m46x805d-6,6s m5m465165d-6,6s
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 13 electrical characteristics (ta=0 70 , vcc=3.3v 0.3v, vss=0v, unless otherwise noted) (note 2) symbol parameter limits parameter symbol m5m46x405d-5s m5m46x805d-5s m5m465165d-5s m5m46x405d-6s m5m46x805d-6s m5m465165d-6s unit min max self refresh ras low pulse width t rass min max ? ns ns t rps t chs 100 104 - 50 100 84 - 50 self refresh ras high precharge time self refresh cas hold time self refresh specifications burst refresh < 128 ms > burst refresh < 128 ms > t ns t sn distributed refresh < 128 ms > distributed refresh < 128 ms > t ns t sn (1) in case of cbr distributed refresh self refresh entry & exit conditions the last / first full refresh cycles must be made within tns / tsn before / after self refresh , on the condition of tns 128 ms and tsn 128 ms. (2) in case of burst refresh the last / first full refresh cycles must be made within tns / tsn before / after self refresh , on the condition of tns 16 ms and tsn 16 ms. self refresh devices are denoted by "s" after speed item, like -5s / -6s . the other characteristics and requirements than the below are same as normal devices. c (ta=0 70 , vcc=3.3v 0.3v, vss=0v, unless otherwise noted see notes 14,15) timing requirements self refresh period self refresh period ~ ~ i cc8 (av) average supply current from vcc extended - refresh cycle (note 5,6) i cc9 (av) average supply current from vcc self - refresh cycle (note 6) c limits min max unit typ test conditions cas before ras refresh cycling tras = tras(min) 500 ? ras = cas 0.2v output = open 400 ? input high level vcc-0.2v 3 input low level 0.2v output = open , trc = 31.25 ? ~ 300ns m5m46x405d-5s,6s m5m46x805d-5s,6s m5m465165d-5s,6s m5m46x405d-5s,6s m5m46x805d-5s,6s m5m465165d-5s,6s
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 14 timing diagrams (note 29) read cycle t rc t ras t rp t rcd t csh t rsh t crp t cah t rah t asr t cdd t dzc t clz t aa t off hi-z t rac t oea t oez t cac hi-z t cas t rad t ral t asr t orh t och t odd t dzo t rcs t asc t rch t rrh row row address address column address t rez t cal t ohr t wez t rdd v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il t crp hi-z data valid t rpc t cpn indicates the don't care input. v ih (min) v in v ih (max) or v il (min) v in v il (max) note 29: indicates the invalid output. indicates the skew of the two inputs. (at m5m465165dxx only) dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ t ohc cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 15 write cycle (early write) t wc t ras t rp t crp t cas t rcd t csh t rsh t crp t wcs t wch t dh t ds t asr t rah t asc t cah hi-z t asr row address data valid column address row address v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il t rpc dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 16 write cycle (delayed write) v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il t wc t ras t rp t crp t cas t rcd t csh t rsh t crp t asr t rah t asc t cah hi-z t rcs t cwl t rwl t wp t dzc t ds t wch t clz hi-z t dzo t odd t oez t oeh t dh t asr row address column address row address hi-z data valid t rpc dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 17 read-write, read-modify-write cycle v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il t rwc t ras t rp t crp t cas t rcd t csh t rsh t crp t asr t rah t asc t cah hi-z t rcs t cwl t rwl t wp t dzc t ds t dzo t odd t oez t oeh t cwd t awd t rwd t aa t oea t rac t rad t asr t dh t clz column address row address data valid t cac hi-z data valid row address hi-z t rpc dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 18 edo mode read cycle t crp t asr t rah t rad t rcd t ras t cp t cac t aa t rac t asr hi-z address row address t cas row t rcs hi-z t dzc t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh t cah t asc t cah t asc t cprh t rch t rrh t cdd t cpa t odd t rez t off t clz t doh t rdd t cac t aa t cpa t doh t cac data valid-3 t aa t cal t cal t cal t ohc t ohr t wez v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il t cah t asc column address-3 column address-2 column address-1 data valid-2 t crp t rpc t rp t oez t ral dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 19 edo mode write cycle (early write) t crp t asr t rah t rcd t cah t ras t cp t asr address row address t rp t cas row t asc t wcs t csh t hpc t cas t cp t cas t rsh t cah t cah t asc t asc hi-z t wch t wcs t wch t wcs t wch data valid-1 data valid-2 data valid-3 t ds t dh t ds t dh t ds t dh t cal t cal t crp v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il column address-1 column address-2 column address-3 t rpc t cal dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 20 edo mode read-write, read-modify-write cycle t dzo t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t hprwc t cas t rwl row address t cah t asc t rcs t rwd t dzc t ds t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t cpwd data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t oez t oeh t rad t cwd t awd t awd t cwd t aa t cac data valid -1 t aa t cac data valid -2 t clz t rac t oea t cpa t oea t odd data valid-1 t crp v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il column address-1 column address-2 row address t rpc t oeh dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 21 edo mode mix cycle (1) (note 30) data valid-2 t dzo t wch t dh t crp t asr t rah t rad t cah t ras t cp t cac t aa t rac hi-z row address t rp t cas t asc t rcs t dzc t dzo t oea t och data valid -1 t csh t hpc t cas t cp t cas t cah t asc t cah t asc t hprwc t cpwd t wp t wcs t ds t clz t cpa data valid -3 t aa t cal t cal t cwd t oez t odd t wez t oeh t oez t clz t oea t asr t crp t cac t odd t dh t ds t rwl t cwl t dzc t awd v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il column address-2 column address-3 column address-1 row address data valid-3 t rpc note 30: oe=l; w hi-z control oe=h; oe hi-z control t wed t rcd dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 22 edo mode mix cycle (2) (note 30) t cpa data valid-1 t cah t asc t hpc data valid-3 t aa t cac t oez t ds t odd data valid-2 hi-z t dh t dzc hi-z t cah t asc t cah t asc t aa t wch t cac t oea t clz hi-z t cpa t cal t cp t cas t rch t wcs t wez t cal t dzc t cas t hcod t haod t hpod t hcwd t hawd t hpwd v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il column address-1 column address-2 column address-3 t wed note 30: oe=l; w hi-z control oe=h; oe hi-z control dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 23 edo mode read cycle (hi-z control by oe) t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z t rp t cas t asc t rcs hi-z t dzc t dzo t oea data valid-1 t csh t hpc t cas t cp t cas t rsh t cah t asc t cah t asc t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t oez t cac data valid-3 t aa t clz hi-z t oepe t chol t oepe t oez t oea t och data valid -1 t ohr t ohc t crp t wez v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il column address-1 row address column address-2 column address-3 row address t rpc dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 24 edo mode read cycle (hi-z control by w) t crp t asr t rah t rad t cah t ras t cp t cac t aa t rac t asr hi-z row address t rp t asc t rcs hi-z t dzc t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh t cah t asc t cah t asc t cprh t ral t rch t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t wez t aa t cac data valid-3 t wpe t rch t rcs t clz hi-z t ohr t ohc t rrh t crp v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il t cas t rcd address column address-1 row column address-2 column address-3 t wez t rpc dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 25 ras-only refresh cycle t crp t asr t rah t ras t rc t asr t crp t rpc t rp row address hi-z row address v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 26 cas before ras refresh cycle t ras t rc t asr t crp t rpc t rp row column address address t rc t ras t csr t chr t csr t rpc t cpn t rch t rcs hi-z t oez t rp t chr t rez t rpc t rrh t off t ohr t ohc v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il t cdd t rsr t rhr t rhr t rsr t odd dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 27 hidden refresh cycle (read) (note 31) note 31: early write, delayed write, read write, or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle shown above. t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t asr t rp hi-z column row address data valid t ras t rc t rp t rsh t asc address t ral hi-z t dzc hi-z t dzo t oea t orh t odd t oez t rez t cdd t rdd t ohr t ohc t off v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il row address t crp t rpc t rrh t rsr t rhr dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 28 self refresh cycle t asr t crp t rpc t rps row address t rass t csr t cpn t rch hi-z t oez t rp t rez t rpc t rrh t off t ohr t ohc v ih v il v oh v ol ras w oe address v ih v il v ih v il v ih v il v ih v il v ih v il t cdd t chs t rsr t rhr dq 1 dq 4 (8,16) (inputs) ~ dq 1 dq 4 (8,16) (outputs) ~ cas lcas / ucas (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 29 upper / (lower) byte read cycle row row address address column address t cac data valid t rc t ras t rp t rcd t csh t rsh t crp t cah t rah t asr t cdd t clz t aa t off hi-z t rac t oea t cas t rad t ral t asr t orh t och t odd t dzo t asc t rch t rrh t rez t cal t ohr t wez t rdd t crp ras w v oh v ol oe lcas (or ucas) ucas (or lcas) v ih v il address v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol hi-z hi-z hi-z t dzc t rcs t oez t rpc t rpc t cpn dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ t ohc (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 30 upper / (lower) byte write cycle (early write) ras w v oh v ol oe lcas (or ucas) ucas (or lcas) v ih v il address v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t wc t ras t rp t crp t cas t rcd t csh t rsh t wcs t wch t asr t rah t asc t cah t asr row address column address row address hi-z hi-z t dh t ds data valid t crp t rpc t crp t rpc dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 31 upper / (lower) byte write cycle (delayed write) ras w v oh v ol oe lcas (or ucas) ucas (or lcas) v ih v il address v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t oez hi-z t wc t ras t rp t crp t cas t rcd t csh t rsh t asr t rah t asc t cah t rcs t cwl t rwl t wp t wch t dzo t odd t oeh t asr column address row address row address hi-z t dzc t ds t dh t clz hi-z data valid hi-z t crp t rpc t crp t rpc dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 32 upper / (lower) byte read-write, upper / (lower) byte read-modify-write cycle. data valid ras w v oh v ol oe lcas (or ucas) ucas (or lcas) v ih v il address v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol hi-z t dzo t oez t oeh t asr t rah t asc t cah t asr t rwc t ras t rp t crp t cas t rcd t csh t rsh t rcs t cwl t rwl t wp t odd t cwd t awd t rwd column address row address row address t dzc t ds t dh t clz t cac t oea hi-z hi-z hi-z data valid t rad t aa t rac t crp t rpc t crp t rpc dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 33 edo mode byte read cycle t asr t rah t rad t cah t asr row address t asc t rcs t cah t asc t cah t asc t cprh t rch t rrh t crp t rcd t ras t cp t rp t cas t csh t hpc t cp t cas t rsh t cal t cal t cal t cac t aa t rac hi-z hi-z t dzc t dzo t oea t och data valid-1 t odd t rez t off t clz t rdd t cpa t doh t cac data valid-3 t aa t ohc t ohr t dzc hi-z t cac t aa t cpa data valid-2 t clz hi-z t cdd t oez t wez ras w v oh v ol oe lcas (or ucas) ucas (or lcas) v ih v il address v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t cas address column address-1 row column address-2 column address-3 t crp t rpc t crp t rpc dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ t ral (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 34 edo mode byte write cycle (early write) t asr t rah t cah t asr address row address row t asc t cah t cah t asc t asc hi-z t crp t ras t rp t csh t hpc t rsh t cal t cal t rcd t cp t cas t cas t cp t cas ras w v oh v ol oe lcas (or ucas) ucas (or lcas) v ih v il address v ih v il v ih v il v ih v il v ih v il v oh v ol data valid-2 t ds t dh v ih v il t ds data valid-1 data valid-3 t dh t ds t dh v ih v il column address-2 hi-z t crp t rpc t crp t rpc dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ t wcs t wch t wcs t wcs t wch v ih v il t wch t cal (at m5m465165dxx only) column address-1 column address-3
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 35 edo mode upper/(lower) byte read-write, upper/(lower) byte read-modify-write cycle t asr t rah t cah t asr t asc t cwl row address t cah t asc t rcs t rwd t crp t ras t cp t rp t csh t rwl t wp t rcs t wp t cwl t cpwd t rad t cwd t awd t awd t cwd hi-z t dzc t ds hi-z hi-z t dh t ds t dzc data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t oez t oeh t aa t cac data valid -1 t aa t cac data valid -2 t clz t rac t oea t dzo t cpa t oea t odd data valid-1 t rcd t cas t hprwc t cas hi-z ras w v oh v ol oe lcas (or ucas) ucas (or lcas) v ih v il address v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol column address-1 column address-2 row address t crp t rpc t rpc t crp dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ t oeh (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 36 upper / (lower) cas before ras refresh cycle ras oe t rp t rc t ras t ras t rp t rc t asr row address t odd t rch ucas (or lcas) lcas (or ucas) address t oez hi-z t off t oez hi-z t cdd v oh v ol v ih v il t cpn t rpc t csr t chr t rpc t crp t csr t chr t rpc v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol w t rpc t rpc t crp t crp t crp t rpc v ih v il t rez t off t ohr t ohc t rsr t rhr t rsr t rhr t rcs ? @ ? @ ? @ ? @ dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 37 upper / (lower) hidden refresh cycle (byte read) (note 31) ras w oe t rc t ras t rp t asr t rah t asc t cah t rcs t ral t rrh t rad t ras t rp t rc t asr t rpc column address row address ucas (or lcas) lcas (or ucas) address t cdd t aa t clz t cac t rac t oea t oez t odd hi-z hi-z data valid t orh t dzo hi-z t dzc row address v oh v ol v ih v il t rpc t crp t rcd t chr t rsh t crp v ih v il t crp t crp v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ohr t ohc t off t rez t off dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ ? @ ? @ ? @ ? @ t rsr t rhr (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s 38 byte self refresh cycle oe t asr row address t odd t rch ucas (or lcas) address t oez hi-z t off t oez hi-z t cdd v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol w t rpc t crp t crp t rpc v ih v il t rez t off t ohr t ohc t rps t rass t rp v ih v il ras t crp t rpc t csr t cpn t rpc v ih v il t chs lcas (or ucas) dq 9 dq 16 (or dq 1 dq 8 ) (inputs) ~ ~ dq 9 dq 16 (or dq 1 dq 8 ) (outputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (inputs) ~ ~ dq 1 dq 8 (or dq 9 dq 16 ) (outputs) ~ ~ ? @ ? @ ? @ ? @ t rsr t rhr (at m5m465165dxx only)
mitsubishi electric aug. 1999 edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram edo mode 67108864-bit (8388608-word by 8-bit) dynamic ram edo mode 67108864-bit (4194304-word by 16-bit) dynamic ram mitsubishi lsis (rev. 1.0) m5m467405/465405dj,dtp -5,-6,-5s,-6s m5m467805/465805dj,dtp -5,-6,-5s,-6s m5m465165dj,dtp -5,-6,-5s,-6s keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive, auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials ?hese materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to mitsubishi electric corporation or a third party. ?itsubishi electric corporation assumes no responsibility for any damage,or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. ?all information contained in these materials,including product data,diagrams and charts, represent information on products at the time of publication of these materials,and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ?mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation,vehicular, medical,aerospace,nuclear,or undersea repeater use. ?he prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. ?f these products or technologies are subject the japanese export control restrictions,they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. ?lease contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. 39

▲Up To Search▲

Price & Availability of M5M467405DTP-5S

	To Download M5M467405DTP-5S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .